Semiconductor Engineering

In-DRAM TRNG Using Simultaneous Multiple-Row Activation (ETH Zurich, CISPA)

DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips” was ...
IEEE

A Novel HDL Code Generator for Effectively Testing FPGA Logic Synthesis Compilers

Abstract: Field programmable gate array (FPGA) logic synthesis compilers (e.g., Vivado, Iverilog, Yosys, and Quartus) are widely applied in electronic design automation (EDA), such as the development ...