Electronic Design

Simulation Mismatches Can Foul Up Test-Pattern Verification

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...
Semiconductor Engineering

Simplifying The Path From Design To Test

Getting an integrated circuit (IC) from design to test is an arduous process that encompasses a number of steps, including: This is an iterative process and can take months, so every step should be ...
Semiconductor Engineering

In-System/In-Field Testing Using High-Quality Deterministic Test Patterns

The amount of electronic content in passenger cars is growing rapidly, primarily due to the integration of advanced safety features. The shift towards fully autonomous vehicles, which must comply with ...
Electronic Design

Using Timing Constraints For Generating At-Speed Test Patterns

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...
InfoWorld

Introduction to design patterns, Part 1: Design pattern history and classification

Get an overview of design patterns, then use what you've learned to evaluate whether the Composite pattern is a good choice for a particular Java use case Numerous strategies have been devised to ...
EDN

Design patterns in SystemVerilog OOP for UVM verification

SystemVerilog supports templates for generic code writing using parameterized classes. Here we’re going to describe some of the design patterns in the code that make up the UVM base class library.