A recent trend has been to convert high-level constructs into FPGA code like Verilog or VHDL. Silice goes the other way: it converts very hardware-specific concepts to Verilog and aims to be a more ...

For this year’s 7400 logic competition, [Nick] decided to build an FPGA out of logic chips (Internet Archive cached version). Perhaps a short explanation is in order to fully appreciate [Nick]’s work.

SynaptiCAD has released an updated version of its timing diagram editor family that simplifies creating the Synopsys Design Constraint (SDC) files used to define the ...

Xilinx employs a new 2.5D Stacked Silicon Interconnect technology to deliver a 6.8 billion transistor FPGA using a passive interposer layer with 10,000 connections between slices. The Virtex-7 2000T ...