Embedded

CPU plus FPGA design flow for software developers: A new tangible reality

Recently, Brian Bailey organized a round table that resulted in a two-part article called Supporting CPUs Plus FPGAs. The experts discussed the evolving reality of systems design based on FPGAs and ...
EDN

Mentor Unveils FPGA Design-Flow Plans

WILSONVILLE, Ore.–May 19, 2003–Mentor Graphics Corporation announced a comprehensive field-programmable gate array (FPGA) design flow that expands traditional FPGA tools with new technologies to ...
EDN

An FPGA design flow for video imaging applications

FPGAs are increasingly being used in a variety of video and image processing applications, primarily due to the increased complexity and performance requirements that such applications demand. This ...
Electronic Design

Agilent FPGA design flow supports AXIe digitizer

June 23, 2014. Agilent Technologies Inc. has announced that the Agilent EEsof EDA W1462 SystemVue FPGA Architect now supports on-board FPGA design and simulation with the Agilent M9703A AXIe wideband ...
Embedded

Tackle team-based FPGA design

You see them at almost every user seminar or industry trade show workshop: the Methodology Managers from XYZ Corporation, who describe the system they use to help the company make sense of the ...
Design-Reuse

Lattice Semiconductor Enables Faster IEC61508 Certification with FPGA Functional Safety Design Flow

Lattice Semiconductor Corporation (NASDAQ: LSCC), the leader in ultra-low power, small form factor, customizable solutions, today announced the availability of the Functional Safety Design ...
Electronic Design

Mentor Graphics, Mathworks Optimize FPGA Design Flow

Mentor Graphics has upgraded its Precision Synthesis tool to include hardware description language (HDL) generated by MathWorks Simulink HDL Coder. Mentor Graphics has upgraded its Precision Synthesis ...
Semiconductor Engineering

Why Your FPGA Synthesis Flow Requires Verification

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...
Semiconductor Engineering

Synopsys FPGA Platform: Enabling Faster Design, Verification and Debug of FPGAs

FPGA development teams are adopting ASIC-style design, verification and debug methodologies. Here are the necessary elements of such a flow. September 11th, 2019 - By: Synopsys Field programmable gate ...
Design-Reuse

FPGA synthesis can be a leverage point in your design flow

FPGA design starts are on the rise due to the lower startup costs and re-programmability that FPGA devices can provide. However, large, complex FPGA devices pose significant challenges to an FPGA ...