Semiconductor Engineering

A New Strategy For Successful Block/Chip Design-Stage Verification

Achieving efficiency in integrated circuit (IC) design while maintaining design quality is not just a goal, but a necessity. Designers constantly strive to strike a balance between ever-tightening ...
Hosted on MSN

Google unveils AlphaChip AI-assisted chip design technology — chip layout as a game for a computer

This week, Google unveiled its AlphaChip reinforcement learning method for designing chip layouts. The AlphaChip AI promises to substantially speed up the design of chip floorplans and make them more ...
Electronic Design

How AI is Supercharging Chip Design Workflows

For decades, the design of leading-edge chips has been a high-wire act—balancing tight deadlines, sophisticated workflows, and the relentless need to consult scattered, often outdated, sources of ...
EDN

Symbiotic EDA Selects Verific Parser Platform as Front End to SoC Synthesis, Formal Verification, FPGA Chip Design Software

Verific Design Automation confirmed that its Parser Platform serves as the front end to Symbiotic EDA‘s system-on-chip (SoC) synthesis, formal verification, and field-programmable gate array (FPGA) ...
Electronic Design

How to Design a Chip for Under $1,000 (Part 1): Book Recommendations

In the first of a multi-part series on how to design a custom chip for under $1,000, our Analog Editor gets you started with a Magnificent 7 list of textbooks. TinyTapeout offers a course that ...